Xilinx FPGA architecture and classification

You must be familiar with Xilinx FPGAs, but FPGAKey still wants to introduce the architecture and classification of Xilinx FPGAs to help you sort out your ideas. At present, mainstream FPGAs all use look-up table architecture based on SRAM technology, and some military and aerospace-grade FPGAs use look-up table architecture based on Flash or fuse and anti-fuse technology.

1. The architecture and function of the lookup table

Look-up--table, or LUT for short is essentially a RAM. Currently, 4-input LUTs are mostly used, so each LUT can be regarded as a RAM with a 4-bit address line. After the user describes a logic circuit through the schematic diagram or HDL, the FPGA development software will automatically calculate all possible results of the logic circuit and write the truth table into RAM in advance. Each input of a signal for logic operation is equivalent to an input of an address Check the table to find out the content corresponding to the address, and then output.

ps:

• The function of LUT to realize the combinational logic is determined by the input, not by the complexity;

• The LUT realizes the combinational logic with a fixed transmission delay.

2. Configurable module (CLB)

Each CLB is connected to a switch matrix for accessing common wiring resources. A CLB contains a pair of slices. A Slice contains 4 6-input lookup tables, 8 flip-flops, multiplexers, and arithmetic carry logic. Connect a slice to form a CLB. The two slices are not directly connected to each other, and each slice is organized by columns.

3. Clock resource and clock management unit

a. Global clock: 7 series FPGAs provide 32 global clock lines with the highest fan-out. The global clock is often driven by CMT, which can completely eliminate the basic distributed delay.

b. Regional clock: An area is defined as any area with 50 I/Os and 50 CLBs high and half the chip width. 7 series FPGA has 8~24 areas. There is 4 clock tracking in each area.

c. I/O clock: I/O clock is very fast, only used for I/O logic and serialization/deserialization circuits. The 7 series provides a direct connection from MMCM to I/O for low-distortion and high-performance interfaces.

d. The clock management tile (CMT) includes a mixed-mode clock manager (MMCM) and a phase lock loop (PLL).

f. Block memory unit: Most FPGAs have built-in RAM, which can be used for high-performance state machines, FIFO buffers, large shift registers, large LUTs, or ROMs.

g. Interconnection resources: Different types of wiring are defined inside the FPGA, which are defined by length. Longer path elements are faster for longer distances

h. Dedicated DSP block: A dedicated and fully customized low-power XtremeDSP DSP48E1 DSP module is integrated into the 7 series FPGA.

i. Input and output blocks:

j. Gigabit transceiver:

k. PCI-E module:

l, XADC module

This is the introduction of Xilinx FPGA structure and classification, I hope it will be helpful to you. Want to learn about Xilinx FPGA products? Welcome to click.